The Custom Layout Techniques course focuses on techniques used in physical design of standard cells and full custom digital block.
SYLLABUS CONTENT:
CMOS Logic process overview
MOS transistor layout
Silicon area reduction techniques
Floorplanning methodologies and techniques
Power routing strategies
COURSE DELIVERY:
Lecture and practical with real-life project
LEARNING OUTCOMES:
Familiarity with the concepts of CMOS logic process
Layout of digital cells
Silicon area reduction techniques
Understanding of custom digital floorplanning methodologies
